Regression modeling for digital test of ΣΔ modulators

The cost of Analogue and Mixed-Signal circuit testing is an important bottleneck in the industry, due to timeconsuming verification of specifications that require state-ofthe- art Automatic Test Equipment. In this paper, we apply the concept of Alternate Test to achieve digital testing of converters. By training an ensemble of regression models that maps simple digital defect-oriented signatures onto Signal to Noise and Distortion Ratio (SNDR), an average error of 1:7% is achieved. Beyond the inference of functional metrics, we show that the approach can provide interesting diagnosis information.Ministerio de Educación y Ciencia TEC2007-68072/MICJunta de Andalucía TIC 5386, CT 30

Random chopping in ΣΔ modulators

Organizado por la Universidad de Zaragoza (Unizar) del 18 al 20 de Noviembre del 2009Σ∆ modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency range. As a result Σ∆ modulators are often the preferred option for sensor and instrumentation. Offset and Flicker noise are usual concerns for this type of applications and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Frequency-shaped random chopping has been pro- posed to minimize the impact of reference voltage interference. It is shown in this paper that the chopper signal is not the only term that modulates the offset and Flicker noise and that unwanted crosstalk can significantly degrade the performance of the modulator.Junta de Andalucía EXC/2005/TIC-927Gobierno de España TEC-2007-6807

Closed-loop Simulation Method for Evaluation of Static Offset in Discrete-Time Comparators

This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.Junta de Andalucía P09-TIC-5386Ministerio de Economía y Competitividad TEC2011-2830

On chopper effects in discrete-time ΣΔ modulators

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.Gobierno de España TEC-2007-68072Consejo Superior de Investigaciones Científicas 200850I21

On-chip evaluation of oscillation-based-test output signals for switched-capacitor circuits

This work presents a simple and low-cost method for on-chip evaluation of test signals coming from the application of the Oscillation-Based-Test (OBT) technique. This method extracts the main test signal features (amplitude, frequency and DC level) in the digital domain requiring just a very simple and robust circuitry. Experimental results obtained from an integrated chip demonstrate the feasibility of the approac

Digital test for the extraction of integrator leakage in first- and second-order ΣΔ modulators

This paper proposes a digital technique to evaluate the integrator leakage within 1st and 2nd order ΣΔ modulators. Integrator leakage is known to be related to the converter precision and belongs to the basic set of design specifications. The technique proposed here involves very few hardware, which makes it specially suitable for Built-In Self-Test (BIST) implementation. Moreover, the integrator leakage evaluation allows its digital correction in cascaded modulators

Characterization and expression of the pseudorabies virus early gene UL54

Pseudorabies virus (PRV) is an alphaherpesvirus, and its gene organization and regulation are similar to the well-characterized human simplex virus (HSV). Sequence analysis of the complete coding region of PRV UL54 gene revealed that the UL54 gene consisted of 1092 nucleotides encoding a protein of 363 amino acids and the gene showed homology to HSV immediate-early protein ICP27. Detection of the UL54 transcript in infected cells by reverse transcription-polymerase chain reaction (RT-PCR) demonstrated that the UL54 gene belonged to the early kinetic class based on sensitivity to cycloheximide, and insensitivity to phosphonoacetic acid (PAA). To study the structure and function of UL54 protein, this gene was subcloned on Escherichia coli expression vector pET28b for overexpression, and the expressed product was applied to generate specific antibody against UL54 protein. The specificity of the mouse immuneserum was confirmed by its ability to react with a 40 kDa viral protein present in the PRV infected cells in Western immunblotting assay, detected as early as 4 h after infection. In addition, immunoperoxidasing staining of PRV infected cells undertaken with this antibody demonstrated mainly nuclear staining pattern. Further-more, the RNA binding potential of UL54 protein was demonstrated by its binding activity to poly(G) RNA homopolymer in Northwestern blotting assay. (C) 2004 Elsevier B.V. All rights reserved